1. Field of the Invention
The present invention relates to a display apparatus used as a display of a personal computer, video camera recorder, digital camera, TV receiver, video projector, and the like, and a circuit for a display device.
2. Related Background Art
Various types of display apparatuses are available. For example, display apparatuses using display devices such as a plasma display, electrochromy display, liquid crystal display, DMD, and the like are known.
Of these apparatuses, a display apparatus using a liquid crystal display will be described below.
A conventional color liquid crystal display apparatus having the arrangement shown in FIG. 17 is known. Referring to FIG. 17, the apparatus comprises a display pixel unit 10, a vertical scanning circuit 20 for the display pixel unit, a sampling switch 30 of an input image signal, a horizontal scanning circuit 40 for the sampling circuit, a line memory 100 for temporarily storing an image signal, and an analog buffer 110 for current-amplifying a signal read out from the line memory.
Each of display pixels on the display pixel unit 10 comprises a switching transistor 11, a liquid crystal 12, and a pixel capacitor 13, as shown in FIG. 18. The gate of the switching transistor 11 is connected to the vertical scanning circuit 20 via a gate line 14, and the input terminal of the switching transistor 11 is connected to the analog buffer 110 via a vertical data line 15. The other terminal of the pixel capacitor 13 is connected to a common electrode line 16, and is applied with a common electrode voltage V.sub.LC.
The sampling switch 30 receives color signals (red, blue, and green) from a signal processing circuit 50 at its input terminal. The signal processing circuit 50 performs correction processing (gamma processing) taking the relationship between the applied voltage and the transmittance (liquid crystal characteristics) into consideration, inverted signal processing for prolonging the service life of a liquid crystal, and the like. A control circuit 60 drives the display apparatus at a predetermined timing.
FIG. 19 shows the arrangement of an inverted signal generation circuit conventionally arranged in the signal processing circuit 50 shown in FIG. 17. FIG. 20 is an output waveform chart of the inverted signal generation circuit shown in FIG. 19. Signal inversion processing in the display apparatus shown in FIG. 17 will be explained below with reference to FIGS. 18 to 20. Referring to FIG. 19, the amplitude of a video signal U.sub.1 is normally about 1 V, and this signal is converted into an inverted signal U.sub.4 whose amplitude (V.sub.H -V.sub.L) is about 10 V, as shown in FIG. 20, so as to drive a liquid crystal. Referring to FIG. 18, the common electrode 16 (V.sub.LC) of the liquid crystal 12 is connected to a common electrode 17 (V.sub.COM) of the pixel capacitor 13, and its common electrode potential V.sub.LCCOM is roughly a middle potential of the inverted signal U.sub.4. In the inverted signal generation circuit shown in FIG. 19, the input video signal U.sub.1 is amplified by an amplifier 51 to positive and negative polarity signals U.sub.2 and U.sub.3 each of which has an amplitude of about 5 V, and these signals are input to level shift circuits 52 and 53. The inverted signal U.sub.4 is generated by alternately switching the output signals of the level shift circuits 52 and 53 in response to control pulses.
A display apparatus in which color filters R, G, and B are arranged on each pixel is known. In order to drive this display apparatus in a non-interlace mode, two methods are available. One method is a double-speed driving method for driving an input video signal S as a doubled frequency signal to write signals in two pixel lines of the display pixel unit, and the other method is a two-system input method having two signal input systems for the display pixel unit.
The above-mentioned inverted signal generation method requires a signal voltage of ten-odd V. The power supply voltage of a normal IC is 5 V. The technical trend is to lower the power supply voltage, and to drive an IC by, e.g., 3.3 V. However, in an existing display apparatus, since a liquid crystal with a high load capacitance is driven by a high-voltage, high-frequency signal, a driving IC is manufactured using an IC having a high withstand voltage and a large p-n junction area. As a result, the IC chip size increases, resulting in high cost and large consumption power. Such an IC cannot be easily applied to the double-speed driving method and a multi-pixel display apparatus with a large number of terminals.
Furthermore, in the case of the two-system input method, the signal level difference between the two systems causes noise such as vertical or horizontal stripes and line flicker. More specifically, in this method, signals are written in two pixel lines using two system inputs. In this case, the level difference between the two pixel lines causes deterioration of image quality in correspondence with the period of an inverted signal. Upon polarity inversion in units of pixel lines, the brightness varies in units of pixel lines, and this variation appears as noise such as vertical or horizontal stripes. In particular, when color pixels have a delta layout, human eyes recognize the level difference between pixels, which are adjacent in the horizontal direction, as a vertical stripe. When the signal polarity is inverted every two pixel lines, the level differences conspicuously appear in units of two lines in turn. In this case, especially, line flicker stands out. This phenomenon is closely associated with the vertical motion of an input image. When the motion of an image becomes close to the field period, the above-mentioned phenomenon becomes conspicuous. According to the experimental results of the present inventors, it is found that the image quality begins to deteriorate when the level difference reaches several ten mV.
It is very difficult to adjust the signal level of several ten mV or less with respect to the signal amplitude of ten-odd V. In consideration of the used temperature conditions and aging, it is conventionally reckoned that such noise cannot be eliminated.
As one of conventional methods, a method of reducing an offset voltage of a buffer circuit at the output side of a memory has been described in Japanese Laid-Open Patent Application No. 4-371997. However, this method changes a voltage at the other terminal of memory means to reduce the offset voltage of the buffer circuit, but does not aim at reducing the amplitude of an input signal to the memory.